DESIGN OF ROUNDING AREA AND POWER EFFICIENT BASED MULTIPLE FOR SIGNED AND UNSIGNED OPERATIONS

DOI: https://doie.org/10.0721/Jbse.2024635798

Srinivasarao Udara, Harish H M, Niranjana Kumara M, Annaiah H,

Keywords:

Computer arithmetic, Floating point, Posit number system, Numerical error, Roba Multiplier.

Abstract:

The IEEE 754 Standard for Floating-Point Arithmetic has been the dominant method for representing real numbers in computer systems for many years. Recently, John L. Gustafson introduced the posit number format, which is touted to offer higher precision using the same or fewer bits and simpler hardware compared to IEEE 754. This new format is suggested as an alternative to the widely used IEEE 754 standard. This research investigates the posit number format, analyzing its features and properties as described in existing literature, and compares it to the standard floating-point numbers. This study evaluates the potential of posits to replace traditional floating-point numbers, as suggested in existing research. A posit arithmetic multiplier is designed at a low level using the Xilinx tool to generate synthesizable Verilog code, which is effective for unsigned number multiplication. Addressing both signed and unsigned numbers is crucial for practical applications. Therefore, we introduce a new method called the RoBA (Rounding Based Approximate) multiplier, which achieves significant reductions in area, delay, and power consumption, by 10%, 40%, and 54%, respectively. To conclude this study, we propose a low-level design for a posit arithmetic RoBA (Rounding Based Approximate) multiplier that supports both signed and unsigned operations. This design is created using the Xilinx tool to produce synthesizable HDL code. The Xilinx ISE 14.3 software is used for this purpose, while the Genus synthesis tool is employed for performing synthesis using 90nm technology, ensuring optimized area and low power consumption.

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